Verilog MCP Server

@kaiwenyu147369

a month ago

Generate Verilog testbenches, lint RTL code (7 rules), and scaffold UVM verification environments — directly inside Claude Code via MCP.

Overview

Features

generate_testbench — Paste a Verilog module, get a complete testbench with clock, reset sequence, DUT instantiation, and VCD dumping.
check_lint — 7 static RTL checks: missing reset, case-without-default, latch inference, width mismatch, blocking assignments in sequential blocks, non-blocking in combinational blocks, and multi-driver detection.
generate_uvm_env — Generate 10 UVM components (interface, transaction, sequence, driver, monitor, agent, scoreboard, environment, test, top) from a single DUT module.

{
  "mcpServers": {
    "verilog-mcp-server": {
      "command": "python",
      "args": [
        "server.py"
      ]
    }
  }
}

Build with ShipAny.