Verilog MCP Server

Name: Verilog MCP Server
Author: kaiwenyu147369

@kaiwenyu147369

关于 Verilog MCP Server

Generate Verilog testbenches, lint RTL code (7 rules), and scaffold UVM verification environments — directly inside Claude Code via MCP.

#verilog #systemverilog #chip-design #eda #uvm #mcp #claude-code #hardware

基本信息

分类

开发工具

传输方式

stdio

发布者

kaiwenyu147369

提交者

Kaiwen Yu

配置

使用下面的配置,将此服务器添加到你的 MCP 客户端。

{
  "mcpServers": {
    "verilog-mcp-server": {
      "command": "python",
      "args": [
        "server.py"
      ]
    }
  }
}

工具

未检测到工具

工具是从 README 中自动提取的。维护者可以在 ## Tools 标题下列出工具,即可填充这部分内容。

概览

What is Verilog MCP Server?

Verilog MCP Server is an MCP (Model Context Protocol) server that provides three tools for Verilog hardware design and verification: testbench generation, static lint checking, and UVM environment generation. It is

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