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Verilog MCP Server

@kaiwenyu147369

Repository

About Verilog MCP Server

Generate Verilog testbenches, lint RTL code (7 rules), and scaffold UVM verification environments — directly inside Claude Code via MCP.

#verilog#systemverilog#chip-design#eda#uvm#mcp#claude-code#hardware

Basic information

Category

Developer Tools

Transports

stdio

Publisher

kaiwenyu147369

Submitted by

Kaiwen Yu

Config

Add this server to your MCP-compatible client using the configuration below.

{
  "mcpServers": {
    "verilog-mcp-server": {
      "command": "python",
      "args": [
        "server.py"
      ]
    }
  }
}

Tools

No tools detected

We auto-extract tools from the README. The maintainer can list them under a ## Tools heading to populate this section.

Overview

What is Verilog MCP Server?

Verilog MCP Server is an MCP (Model Context Protocol) server that provides three tools for Verilog hardware design and verification: testbench generation, static lint checking, and UVM environment generation. It is

Comments

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